1. Field
Aspects of the present disclosure relate to semiconductor devices, and more particularly to half-node scaling for vertical structures.
2. Background
As integrated circuit (IC) technology advances, device geometries are reduced. Between major “full-node” technology transitions, device designers utilize device reduction within a mature technology node. Such device size reductions may be called “half-node” scaling.
In half-node scaling, the area of a device on a chip is reduced in two dimensions, (i.e., x and y) by a certain amount. The half-node scaled version occupies less die area and thus more copies of the IC can be produced for each wafer. This reduces costs because additional devices are produced without changing the layout design, and the original device models may be used to model the reduced-size circuit.
However, with vertical structures, such as fin-structured field-effect transistors (FinFETs), reducing the height (z) of the fin structure would require a new simulation model. As such, half-node scaling is avoided in vertical structure designs. Further, even planar designs may have portions of the devices, such as interconnect line traces, which are at the limit of the lithography processes for a given node. Half-node scaling of such devices would require new layouts and offset cost savings available in half-node scaling processes.